III-V elements may be advantageous in certain applications for silicon-based devices, for example, channel materials due to high electron mobility and source/drain materials due to low contact resistance and the ability to function as a stressor for mobility enhancement in silicon-based devices. As such, research has been undertaken concerning the deposition of III-V materials on III-V substrates. However, given the expense of III-V substrates, these applications are often associated with lacking cost effectiveness. Defects during heteroepitaxy of III-V elements on silicon arise from material incompatibilities such as large lattice mismatch (>4%), valency difference, thermal property differences, and conductivity differences. The defects may include dislocations, anti-phase boundaries, and stacking faults for III-V layers. III-V features are frequently formed in trenches or blanketed on substrates. Although beneficial with smaller device size requirements, III-V element growth inside high aspect ratio (depth vs. opening width) trenches becomes increasingly difficult.
III-V element channels are generally formed in an array of nanometer scale planar or vertical structures with critical dimensions of about 5-15 nm and depths of about 20-100 nm. High quality III-V element channels have minimal defects (<105/cm2), consistent and controlled composition and morphology, and no parallel conduction of carriers other than in the active device region of the channel structures. Minimal current leakage and charge accumulation within the channels are desired to improve performance of the microelectronic device. Current buffer structures using GaAs/InP or GaAs/InAlAs are generally too thick (>1 μm) to be cost effective and do not provide adequate current leakage control. Given the inherent difficulties associated with forming III-V layers on silicon, achieving high quality III-V element channels presents a substantial challenge.
Thus, what is needed in the art is a structure for III-V materials on silicon that provides desirable characteristics and improved performance over current III-V structures.